BIM (TU) Question Paper 2014 – Digital Logic Design | First Semester

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Digital Logic DesignOld Question Paper 2014 – Digital Logic Design
BIM / First Semester / IT 212: Digital Logic Design
Tribhuvan University | Faculty of Management

Office of the Dean
Full Marks: 40 | Time: 2 Hrs

Group “A” – Brief Answer Questions: [10 X 1= 10]

1. Differentiate periodic and non periodic wave.
2. Decimal numbers are weighted numbers. Justify.
3. What is the number of selection lines if multiplexer have 1234 input lines?
4. How many Flip-flops are required to divide a frequency by 16?
5. Is it possible to implement counting function using data flip flop? Support your answer.
6. If the state of 4-bit Johnson counter is 1100, what is its state after 4th clock pulse?
7. How sizes of data register and address register are calculated in computer system?
8. Write advantages of PLA over ROM.
9. Explain any two operational characteristics of an IC.
10. Define Excitation table.

Group “B” – Short Answer Questions: [5 X 4 = 20]

11. (a) If A = 1510 and B = 1210 computer B – A and A + B by converting them to binary system.
(b) Verify any one De Morgan’s law for three variables using Truth Table.
12. Design circuit diagram for code converter.
13. Construct MOD – 8 asynchronous up down counter with timing diagram.
14. Discuss flip flop operating characteristics.
15. If you have five bit of data to insert into a shift register all at once and you need to extract these data one bit at a time, which shift register will you suggest? Design a circuit diagram for your selection and explain its operation.

Group “C” – Long Answer Questions: [2 X 5 = 10]

16. If F(A, B, C, D) = Ʃ (3, 4, 7, 8, 14) and d(A, B, C, D) = Ʃ(1, 6, 9, 13) design a truth table for this expression and design a circuit using
a. Using Basic gates
b. Using minimum number of NAND gates.

17. Analyze the following sequential circuit.

Digital Logic Design Figure 1

Posted By : Hari Prasad Chaudhary | Comment RSS | Category : Bachelor Level, Tribhuvan University
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